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We studied the impact of grain boundary (GB) protrusion on the electrical properties of low temperature polycrystalline silicon thin film transistors. The analysis of atomic force microscopy and transmission electron microscopy images indicate the grain size of ~350 nm and a protrusion height of ~35 nm. The transfer and output characteristics are well fitted by technology computer-aided design using two different density of states for poly-Si grain and GB, respectively. From 2-D contour mapping, a drastic reduction of hole concentration (~5 x 10¹⁶ cm^-3) at GB protrusion site was obtained as compared to the grain (~3 x 10¹⁸ cm^-3). Trapping concentration at GB is much higher, which leads to the reduction in the mobility.