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This paper presents a cost-effective hybrid low drop-out regulator (LDO) circuitry for state-of-the-art DDR DRAM cores that not only supports various refresh operations, but also meets the JEDEC specification of the refresh period by improving the load-transient response. In order to guarantee a stable output voltage by achieving the precise off-control operation, a load replication circuit with dummy DRAM cells is exploited. The proposed cost-effective LDO has been implemented and fabricated in a standard 180nm CMOS technology and occupies 0.165mm2. By adopting the hybrid LDO, voltage droop improvements of 62mV and 110mV, and <inline-formula> <tex-math notation="LaTeX">$t_{RFC}$ </tex-math></inline-formula> gain of 100ns and 120ns are measured with refresh rates of 4K and 8K, respectively. The measured current consumption overhead by 8 hybrid LDOs is <inline-formula> <tex-math notation="LaTeX">$36\mu \text{A}$ </tex-math></inline-formula> during the 8K refresh operation. The peak current efficiency is 99.6&#x0025; at a supply voltage of 1.2V.