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For the first time, the electrothermal characteristics of a three-dimensional (3D) monolithic complementary FET (CFET) in DC operation as well as in AC CMOS operation were investigated with TCAD simulations. The self-heating effect (SHE) in a monolithic CFET is expected to be a critical problem given its highly compact architecture. DC analysis of the individual NFET and PFET devices revealed that increasing the channel width from 5.0 to 7.0 nm improved the thermal resistance up to 8.5&#x0025; and the <italic>RC</italic> delay up to 9.6&#x0025;, while greatly deteriorating the on/off ratio. AC CMOS inverter simulations of the CFET showed that reducing the NFET/PFET vertical separation from 30 to 10 nm resulted in 11.9&#x0025; faster operation frequency and 3.4&#x0025; reduced dynamic power loss, but 11.2&#x0025; higher rise in device temperature. The clear trade-off relationships between the thermal and electrical performance factors necessitate optimization of the device dimension parameters. These findings are expected to provide critical insight for the design technology co-optimization (DTCO) in the 3-nm regime.