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<p>Abstract</p> <p>Previously, a damascene process based on nanoimprint lithography has been proposed (Schmid G M, et al. in J Vac Sci Technol B 24(3) 1283, 2006) to greatly reduce the fabrication steps of metal interconnection in integrated circuit. For such a process to become a viable technique, a mold having two pattern levels with precise alignment between them must be fabricated first. To this end, this work demonstrates a &#8220;self-aligned&#8221; fabrication process where the two pattern levels would be perfectly aligned if ignoring the noise during e-beam writing. The process is based on one EBL on a bi-layer resist stack, with the sensitivity for the top layer much higher than that of the bottom layer, which enables separate pattern transfer of the two pattern levels. Using ZEP-520A and poly(dimethylglutarimide) (PMGI) resists, we fabricated pillars having a diameter of 150 nm sitting on ridges having a width of 1.5 &#956;m, which can be used to create via-holes and trenches for IC interconnect by nanoimprint lithography. The current process can also find applications in other areas that require two-level patterning with precise alignment between them.</p>