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Shared-memory systems enable parallel computing for the automatic test pattern generation (ATPG). Although the existing techniques for parallel ATPG reach near-linear speedup, test inflation becomes a common problem in its practicality. Therefore, this paper proposes a multi-threaded test pattern generation called <italic>MT-TPG</italic> that can suppress test inflation and accelerate fault processing, simultaneously, to retain high parallelism. For suppressing test inflation, <italic>hard-fault shuffling</italic> (<italic>HFS</italic>) and <italic>concurrent-fault interruption</italic> (<italic>CFI</italic>) are involved to avoid repeated detection of the same fault among different threads. For accelerating fault processing, the <italic>potentially-droppable-fault removal</italic> (<italic>PDFR</italic>) and <italic>single-pattern parallel-fault simulation</italic> (<italic>SPPFSim</italic>) collectively drop not-yet-detected faults as early as possible for shortening the overall execution time of ATPG. According to our experimental results, the <italic>HFS</italic> and <italic>CFI</italic> can successfully suppress test inflation to &#x003C; 4&#x0025; on 17 benchmark circuits; <italic>PDFR</italic> and <italic>SPPFSim</italic> can achieve 13.7X speedup using 16 threads on average. As a result, <italic>MT-TPG</italic> is proven effective at unleashing parallelism with minimal test inflation on shared-memory systems.