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Negative-capacitance field-effect transistors (NC-FETs) are significantly affected by their ferroelectric (FE)/dielectric (DE) phase configurations owing to the uncertainty of their crystalline phases. This study presents an analysis of random FE/DE grain distribution-induced variations from multiple perspectives using a seed random number generator in a technology computer-aided design (TCAD) simulation. The results obtained for the NC fully depleted silicon-on-insulator (NC-FDSOI) FETs indicate that device variations can be effectively reduced by increasing the probability of FE grains which improves the switching characteristics. Additionally, the FE distribution at the source presents a larger ON-state current (Ion), while the complete DE path from the source to the drain presents a larger OFF-state current (Ioff). The simulation results also demonstrate that reducing the lateral grain size reduces the device variations while improving the switching current ratio. Increasing the ferroelectric layer thickness of the NC-FDSOI FET can improve its switching performance; however, this also increases its variations. The random FE/DE distribution-induced variations can be reduced by adequately increasing the gate width through device scaling.