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This paper presents a combined two-dimensional word-based serial-in/serial-out systolic processor for field multiplication and squaring over GF(2m) to improve hardware utilization and power consumption. The proposed processor is extracted by applying non-linear scheduling and projection functions to the algorithm dependency graph. The extracted processor features scalability that gives the designer more flexibility to control the processor size and the execution time. ASIC Implementation results of the proposed combined two-dimensional word-serial design and the best existing designs show that the proposed structure realizes a considerable saving in the area and consumed energy up to 93.7% and 98.2%, respectively. This makes it more suitable for restricted implementations of cryptographic primitives in resource-constrained consumer electronics devices such as hand-held devices, wearable and implantable medical devices, smart cards, wireless sensor nodes, restricted nodes in the Internet of Things (IoT), and radio frequency identification (RFID) devices.