Al<sub>2</sub>O<sub>3</sub> Layers Grown by Atomic Layer Deposition as Gate Insulator in 3C-SiC MOS Devices

oleh: Emanuela Schilirò, Patrick Fiorenza, Raffaella Lo Nigro, Bruno Galizia, Giuseppe Greco, Salvatore Di Franco, Corrado Bongiorno, Francesco La Via, Filippo Giannazzo, Fabrizio Roccaforte

Format: Article
Diterbitkan: MDPI AG 2023-08-01

Deskripsi

Metal-oxide-semiconductor (MOS) capacitors with Al<sub>2</sub>O<sub>3</sub> as a gate insulator are fabricated on cubic silicon carbide (3C-SiC). Al<sub>2</sub>O<sub>3</sub> is deposited both by thermal and plasma-enhanced Atomic Layer Deposition (ALD) on a thermally grown 5 nm SiO<sub>2</sub> interlayer to improve the ALD nucleation and guarantee a better band offset with the SiC. The deposited Al<sub>2</sub>O<sub>3</sub>/SiO<sub>2</sub> stacks show lower negative shifts of the flat band voltage V<sub>FB</sub> (in the range of about −3 V) compared with the conventional single SiO<sub>2</sub> layer (in the range of −9 V). This lower negative shift is due to the combined effect of the Al<sub>2</sub>O<sub>3</sub> higher permittivity (ε = 8) and to the reduced amount of carbon defects generated during the short thermal oxidation process for the thin SiO<sub>2</sub>. Moreover, the comparison between thermal and plasma-enhanced ALD suggests that this latter approach produces Al<sub>2</sub>O<sub>3</sub> layers possessing better insulating behavior in terms of distribution of the leakage current breakdown. In fact, despite both possessing a breakdown voltage of 26 V, the T-ALD Al<sub>2</sub>O<sub>3</sub> sample is characterised by a higher current density starting from 15 V. This can be attributable to the slightly inferior quality (in terms of density and defects) of Al<sub>2</sub>O<sub>3</sub> obtained by the thermal approach and, which also explains its non-uniform dC/dV distribution arising by SCM maps.