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<p/> <p>This paper proposes a parameterized digital signal processor (DSP) core for an embedded digital signal processing system designed to achieve demodulation/synchronization with better performance and flexibility. The features of this DSP core include parameterized data path, dual MAC unit, subword MAC, and optional function-specific blocks for accelerating communication system modulation operations. This DSP core also has a low-power structure, which includes the gray-code addressing mode, pipeline sharing, and advanced hardware looping. Users can select the parameters and special functional blocks based on the character of their applications and then generating a DSP core. The DSP core has been implemented via a cell-based design method using a synthesizable Verilog code with TSMC 0.35 <inline-formula><graphic file="1687-6180-2003-232360-i1.gif"/></inline-formula>m SPQM and 0.25 <inline-formula><graphic file="1687-6180-2003-232360-i2.gif"/></inline-formula>m 1P5M library. The equivalent gate count of the core area without memory is approximately 50 k. Moreover, the maximum operating frequency of a <inline-formula><graphic file="1687-6180-2003-232360-i3.gif"/></inline-formula> version is 100 MHz (0.35 <inline-formula><graphic file="1687-6180-2003-232360-i4.gif"/></inline-formula>m) and 140 MHz (0.25 <inline-formula><graphic file="1687-6180-2003-232360-i5.gif"/></inline-formula>m).</p>