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Deformation potential (D_ac), which is one of the most important parameters determining the rate of electron-acoustic phonon scattering, in Si around MOS interfaces is thoroughly studied with regard to the dependences on surface carrier densities, back-gate biases, and device structures. It is demonstrated that D_ac increases sharply at the MOS interface. To investigate the impact of the increased D_ac on μ_e, thick body-channel SOI MOSFETs, where drain current flows in the entire SOI layers, was fabricated. The carrier transport experiments reveal that μ_e of greater than 1100 cm² V^-1 s^-1 is obtained in body-channel SOI MOSFETs with the SOI thickness of greater than 70 nm. By taking into account the Dac profile around the MOS interface, experimental μ_e of SOI MOSFETs is numerically reproduced over a wide range of SOI thicknesses. μ_e of the body-channel SOI MOSFETs is also well reproduced using the same D_ac profile. Thus, it is concluded that D_ac increases sharply at the Si/SiO₂ interface. The accurate modeling of the increased D_ac around the Si/SiO₂ interface is indispensable for designing high-performance and/or low-power 3-D MOSFETs including FinFETs, extremely thin SOI MOSFETs, and nanowire MOSFETs, because these types of MOSFETs have greater interface-to-volume ratios.