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In a world of miniaturized electronics, there is a rapidly increasing need for reliable, efficient, and compact energy storage systems with low-loss dielectrics. To address this need, this work proposes the development of compact, micro-capacitive energy storage devices compatible with IC processing so that they can be integrated monolithically on-chip. There are two main approaches to the fabrication of integrated on-chip micro-supercapacitor energy storage devices: interdigitated electrode (IDE) devices and parallel plate electrode (PPE) devices. As part of the design of such systems, this study aims to investigate the behavior of current density-voltage (J-V) in homogeneous and heterogeneous IDE and PPE devices to determine whether the anomalies between the interfaces of dielectric materials in such structures affect their leakage current. The ultimate goal is to design a solid-state capacitor energy storage module with low-loss dielectrics, high energy densities, and improved areal capacitance density that can offer a high number of charge/discharge cycles for portable power electronics. An understanding of J-V characteristics is crucial in achieving this objective. Specifically, this paper will explore and investigate nanolaminate, solid-state PPE, and IDE capacitive energy storage “modules” fabricated using nanolithographic techniques. The dielectric layers in these structures are composed of alternating nanolaminate layers of thin higher-k Al<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msub><mrow></mrow><mn>2</mn></msub></semantics></math></inline-formula>O<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msub><mrow></mrow><mn>3</mn></msub></semantics></math></inline-formula> and lower-k SiO<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msub><mrow></mrow><mn>2</mn></msub></semantics></math></inline-formula>. Recent findings have shown that capacitive energy storage devices made from a large number of these on-chip multilayer nanolaminate energy storage PPE (MNES-PPE) structures that utilize the interfacial anomalies of thin high-k/SiO<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msub><mrow></mrow><mn>2</mn></msub></semantics></math></inline-formula> nanolaminates could have the potential to overcome many of the limitations of current compact energy storage technologies. Preliminary projections indicate that these high-density nanolaminate capacitors with laminate thicknesses around 5 nm could produce devices with high volumetric energy densities (<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mo>∼</mo><mn>290</mn></mrow></semantics></math></inline-formula> J/cm<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msup><mrow></mrow><mn>3</mn></msup></semantics></math></inline-formula>) that are significantly higher than conventional supercapacitors (<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mo>∼</mo><mn>20</mn></mrow></semantics></math></inline-formula> J/cm<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msup><mrow></mrow><mn>3</mn></msup></semantics></math></inline-formula>).