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As the scale of graphene‐based non‐volatile memory is reduced, the ratio of access resistance RA to total channel resistance RTOT is increased. To investigate the effect of the RA on I–V characteristics, we fabricated devices with various access lengths LA and self‐aligned structure. Proposed structure using self‐aligned gate minimises LA, and thereby improves the drain current, ‘on/off’ current ratio ION/IOFF and transfer characteristics. In proposed structure, ‘off’ current is increased from 0.16 to 0.28 mA because RTOT was reduced; ‘on’ current increased from 0.35 to 0.72 mA, but ION/IOFF increased from 2.18 to 2.57. Proposed structure also had larger memory window (8.5 V) than did conventional devices (6.7 V).