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We show a pulse-efficient circuit transpilation framework for noisy quantum hardware. This is achieved by scaling cross-resonance pulses and exposing each pulse as a gate to remove redundant single-qubit operations with the transpiler. Crucially, no additional calibration is needed to yield better results than a CNOT-based transpilation. This pulse-efficient circuit transpilation therefore enables a better usage of the finite coherence time without requiring knowledge of pulse-level details from the user. As demonstration, we realize a continuous family of cross-resonance-based gates for SU(4) by leveraging Cartan's decomposition. We measure the benefits of a pulse-efficient circuit transpilation with process tomography and observe up to a 50% error reduction in the fidelity of R_{ZZ}(θ) and arbitrary SU(4) gates on IBM Quantum devices. We apply this framework for quantum applications by running circuits of the quantum approximate optimization algorithm applied to MAXCUT. For an 11-qubit nonhardware native graph, our methodology reduces the overall schedule duration by up to 52% and errors by up to 38%.