Performance Improvement of Spacer-Engineered N-Type Tree Shaped NSFET Toward Advanced Technology Nodes
oleh: Ummadisetti Gowthami, Asisa Kumar Panigrahy, Depuru Shobha Rani, Muralidhar Nayak Bhukya, Vakkalakula Bharath Sreenivasulu, M. Durga Prakash
| Format: | Article |
|---|---|
| Diterbitkan: | IEEE 2024-01-01 |
Deskripsi
Tree-shaped Nanosheet FETS (NSFET) is the most dependable way to scale down the gate lengths deep. This paper investigates the 12nm gate length (LG) n-type Tree-shaped NSFET with the gate having a stack of high-<inline-formula> <tex-math notation="LaTeX">$k$ </tex-math></inline-formula> dielectric (HfO2) and SiO2 using different spacer materials, which can be done using TCAD simulations. The Tree-shaped NFET device with <inline-formula> <tex-math notation="LaTeX">${\mathrm {T}}_{\mathrm {(NS)}} =5$ </tex-math></inline-formula> nm, <inline-formula> <tex-math notation="LaTeX">${\mathrm {W}}_{\mathrm {(NS)}} =25$ </tex-math></inline-formula> nm, <inline-formula> <tex-math notation="LaTeX">${\mathrm {W}}_{\mathrm {IB}} =5$ </tex-math></inline-formula> nm, and <inline-formula> <tex-math notation="LaTeX">${\mathrm {H}}_{\mathrm {IB}} =25$ </tex-math></inline-formula> nm has high on-current (<inline-formula> <tex-math notation="LaTeX">$I_{ON}$ </tex-math></inline-formula>) and low off-current (<inline-formula> <tex-math notation="LaTeX">$I_{OFF}$ </tex-math></inline-formula>). The 3D device with single-<inline-formula> <tex-math notation="LaTeX">$k$ </tex-math></inline-formula> and dual-k spacers are compared and its DC characteristics are shown. It is noted that the dual-<inline-formula> <tex-math notation="LaTeX">$k$ </tex-math></inline-formula> device achieves the maximum <inline-formula> <tex-math notation="LaTeX">$I_{ON}/I_{OFF}$ </tex-math></inline-formula> ratio, which is <inline-formula> <tex-math notation="LaTeX">$10^{9}$ </tex-math></inline-formula>, compared to <inline-formula> <tex-math notation="LaTeX">$10^{7}$ </tex-math></inline-formula> because the fringing fields with spacer dielectric lengthen the effective gate length. Additionally, the impact of work function, interbridge height, width, gate lengths, and temperature, along with the device’s analog/RF and DC metrics, is also investigated in this paper. Even at 12 nm LG, the proposed device exhibits good electrical properties with DIBL =23 mV/V and SS =62 mV/dec and switching ratio (<inline-formula> <tex-math notation="LaTeX">$I_{ON}/I_{OFF}) = 10^{9}$ </tex-math></inline-formula>. The device’s performance confirms that Moore’s law holds even for lower technology nodes, allowing for further scalability.