Find in Library

The present research work represents the numerical study of the device performance of a lead-free Cs₂TiI_6−XBr_X-based mixed halide perovskite solar cell (PSC), where x = 1 to 5. The open circuit voltage (V_OC) and short circuit current (J_SC) in a generic TCO/electron transport layer (ETL)/absorbing layer/hole transfer layer (HTL) structure are the key parameters for analyzing the device performance. The entire simulation was conducted by a SCAPS-1D (solar cell capacitance simulator- one dimensional) simulator. An alternative FTO/CdS/Cs₂TiI_6−XBr_X/CuSCN/Ag solar cell architecture has been used and resulted in an optimized absorbing layer thickness at 0.5 µm thickness for the Cs₂TiBr₆, Cs₂TiI₁Br₅, Cs₂TiI₂Br₄, Cs₂TiI₃Br₃ and Cs₂TiI₄Br₂ absorbing materials and at 1.0 µm and 0.4 µm thickness for the Cs₂TiI₅Br₁ and Cs₂TiI₆ absorbing materials. The device temperature was optimized at 40 °C for the Cs₂TiBr₆, Cs₂TiI₁Br₅ and Cs₂TiI₂Br₄ absorbing layers and at 20 °C for the Cs₂TiI₃Br₃, Cs₂TiI₄Br₂, Cs₂TiI₅Br₁ and Cs₂TiI₆ absorbing layers. The defect density was optimized at 10¹⁰ (cm⁻³) for all the active layers.