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Both large current capability and strong short-circuit (SC) ruggedness are necessary for 3.3 kV SiC MOSFETs to improve system efficiency and reduce costs in industrial and traction applications. In this paper, the effects of Junction Field Effect Transistor (JFET) region width and JFET doping (JD) on conduction and SC capability of the 3.3 kV planar-gate SiC MOSFETs are systematically investigated by experiments and simulations. When the JFET width (W_JFET) of device without JD is smaller, the positive temperature coefficient of the special on-resistance (R_on,SP) is larger. The JD is effective to improve the R_on,SP, but excessive electric field in gate oxide induced by JD should be paid more attention. The optimization of W_JFET can be used to improve both R_on,SP and short circuit withstanding time (SCWT) at the same time. The drain-source current (I_ds) and SCWT of the optimized devices are 50 A and more than <inline-formula> <tex-math notation="LaTeX">$20~{\mu }\text{s}$ </tex-math></inline-formula>, respectively, which is state-of-the-art for 3.3 kV SiC MOSFETs.