Find in Library

This paper presents an energy-saving and high-resolution successive approximation register (SAR) analog-to-digital converter (ADC) with 14-nm CMOS FinFET technology for wireless communication system. An Equivalent Split-Capacitor is proposed to enlarge redundancy range and alleviate the settling error of the bridge capacitor array. A hybrid capacitor switching procedure is adopted to reduce power consumption and the variation of input common-mode voltage of the comparator. Measurement results of the 14-nm CMOS SAR-ADC achieves a SNDR of 61.29 dB and 58.34dB at low and Nyquist input frequency, respectively, resulting in figure-of-merits(FoMs) of 8.2 and 11.15fJ/conversion-step, respectively. The ADC core occupies an active area 0.112mm².