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In today’s world as the need of memory elements with high performance are highly demanded, so flip flops came into existence. The flip flops have many applications in the field of electronics. The design of these flip flops is highly important for research area nowadays due to greater demand in small portable devices. There is a need of attention to reduce the power dissipation with increase in demand of small portable devices. Leakage power dissipation is the main challenge in the VLSI technology. In this paper, delay flip flop (DFF) is designed with ON/OFF (ONOFIC) approach. ONOFIC approach is an energy efficient method for designing CMOS logic circuit, as it gives good agreement between propagation delay and power dissipation. This approach decreases the power dissipation to a high extent. The ONOFIC design of D flips flop and master slave D flip-flop is compared with the conventional design for various parameters. Monte Carlo analysis is done for delay metrics for 400 runs. Low power delay product (PDP) and propagation delay is the outcome of this new design.