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This paper introduces a voltage reference design able to operate over the wide supply voltage range from 1.8 V down to 0.2 V, and pW power. To mitigate the effect of global variations (e.g., die-to-die, wafer-to-wafer), the proposed NMOS-only architecture introduces process sensor-driven selection/merging of circuit replicas at boot (or run) time. Being the circuit replicas optimized for different process corners, their selection or merging fundamentally relaxes the traditionally conflicting design tradeoffs that affect the overall voltage accuracy in deep sub-threshold, while not requiring any testing-time trimming or non-volatile memory process option for low-cost applications. Measurements of a 180-nm test chip across 45 dice from different corner wafers demonstrate reliable operation down to 0.2 V with 3.9-pW power consumption at room temperature. The proposed process sensor-driven replica selection is shown to enable 1.6&#x0025; <inline-formula> <tex-math notation="LaTeX">$V_{REF}$ </tex-math></inline-formula> process sensitivity (i.e., <inline-formula> <tex-math notation="LaTeX">$\sigma/\mu)$ </tex-math></inline-formula>, 34.9-<inline-formula> <tex-math notation="LaTeX">$\mu \text{V}/^{\circ }\text{C}$ </tex-math></inline-formula> (819-ppm/&#x00B0;C) mean temperature coefficient, and 60.7-<inline-formula> <tex-math notation="LaTeX">$\mu \text{V}$ </tex-math></inline-formula>/V (0.14-&#x0025;/V) mean line sensitivity across process corners. The resulting 1.4-mV overall absolute accuracy of the reference voltage across dice and corner wafers (1-<inline-formula> <tex-math notation="LaTeX">$\sigma$ </tex-math></inline-formula>), voltage fluctuations (0.3 V) and temperature deviation (20&#x00B0;C) is improved by <inline-formula> <tex-math notation="LaTeX">$1.9\times $ </tex-math></inline-formula> compared to the case without replica selection, and by 3-<inline-formula> <tex-math notation="LaTeX">$15.4\times $ </tex-math></inline-formula> compared to prior references with sub-nW consumption.