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The continuous demand for small portable electronics is pushing the semiconductor industry to develop novel lithographic methods to fabricate the elementary structures for microelectronics devices with dimensions below 10 nm. Top-down strategies include multiple patterning photolithography, extreme ultraviolet lithography (EUVL), electron beam lithography (EBL), and nanoimprint lithography. Bottom-up approaches mainly rely on block copolymers (BCPs) self-assembly (SA). SA of BCPs is extremely appealing due to its excellent compatibility with conventional photolithographic processes, high-resolution patterns, and low process costs. Among the various BCPs, the polystyrene-b-polydimethylsiloxane (PS-b-PDMS) represents the most investigated material for the fabrication of sub-10 nm structures. However, PS-b-PDMS cannot be easily processed by conventional thermal treatments due to its slow SA kinetic coupled with a relatively low thermal stability. This review focuses on the available annealing methods to promote the SA PS-b-PDMS in parallel-oriented cylindrical sub-10 nm structures. Moreover, literature data regarding the annealing time, defects density, line edge roughness (LER) and line width roughness ( LWR) are discussed with reference to the stringent requirements of semiconductor technology.