Find in Library
Search millions of books, articles, and more
Indexed Open Access Databases
A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process
oleh: Meng-Yin Hsu, Chu-Feng Liao, Yi-Hong Shih, Chrong Jung Lin, Ya-Chin King
Format: | Article |
---|---|
Diterbitkan: | SpringerOpen 2017-06-01 |
Deskripsi
Abstract This paper reports a novel full logic compatible 4T2R non-volatile static random access memory (nv-SRAM) featuring its self-inhibit data storing mechanism for in low-power/high-speed SRAM application. With compact cell area and full logic compatibility, this new nv-SRAM incorporates two STI-ReRAMs embedded inside the 4T SRAM. Data can be read/write through a cross-couple volatile structure for maintaining fast accessing speed. Data can be non-volatilely stored in new SRAM cell through a unique self-inhibit operation onto the resistive random access memory (RRAM) load, achieving zero static power during data hold.