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Mathematically secure cryptographic algorithms leak significant side-channel information through their power supplies when implemented on a physical platform. These side-channel leakages can be exploited by an attacker to extract the secret key of an embedded device. The existing state-of-the-art countermeasures mainly focus on power balancing, gate-level masking, or signal-to-noise (SNR) reduction using noise injection and signature attenuation, all of which suffer either from the limitations of high power/area overheads, throughput degradation or are not synthesizable. In this article, we propose a generic low-overhead digital-friendly power SCA countermeasure utilizing a physical Time-Varying Transfer Function (TVTF) by randomly shuffling distributed switched capacitors to significantly obfuscate the traces in the time domain. We evaluate our proposed technique utilizing a MATLAB-based system-level simulation. Finally, we implement a 65nm CMOS prototype IC and evaluate our technique against power side-channel attacks (SCA). System-level simulation results of the TVTF-AES show <inline-formula> <tex-math notation="LaTeX">$\sim 5000\times $ </tex-math></inline-formula> minimum traces to disclosure (MTD) improvement over the unprotected implementation with <inline-formula> <tex-math notation="LaTeX">$\sim 1.25\times $ </tex-math></inline-formula> power and <inline-formula> <tex-math notation="LaTeX">$\sim 1.2\times $ </tex-math></inline-formula> area overheads, and without any performance degradation. SCA evaluation with the prototype IC shows <inline-formula> <tex-math notation="LaTeX">$3.4M$ </tex-math></inline-formula> MTD which is <inline-formula> <tex-math notation="LaTeX">$500\times $ </tex-math></inline-formula> greater than the unprotected solution.