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<p>Design layout 1-stage pipeline is part of the 8-stage pipeline 80 Msps ADC. Layout 1-stage pipeline consists <br />of 3 units : op-amp, switch capacitor, precision comparator with latch. Pipeline ADC works gradually and requires <br />synchronization of digital output 8 stage by using a unit delay circuit (D-FF). Pipeline ADC requires pulse rate (clock)<br />generator to support its work. Units OP-AMP transconductance CMOS components designed with the correct <br />specification ADC applications with capacitive loads, with a large input impedance and minimize noise. The precision <br />comparator has Vos<br />(offset voltage) approximately equal to 0V. The capacitor switch designs use NMOS switch as a <br />switch for the sampling and multiplying. In the sampling phase and multiplying processes, the ADC requires a clock <br />pulse with a non-intersect mode (lapping). The width of non-overlapping period was adjusted to the time of constance <br />in the sampling process and multiplying. The total number of each pulse period equal to 12.5 ns or equal to the <br />frequency of 80MHz. In the 1-stage layout an additional correction capacitor was required to correct residual voltage. <br />The total area of the layout 1-stage pipeline ADC is 1-bit 200 μm x 98μm.</p>