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A new cell topology named the dodecagonal (a polygon with twelve sides, short for Dod) cell is proposed to optimize the gate-to-drain capacitance (<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msub><mi mathvariant="normal">C</mi><mi>gd</mi></msub></semantics></math></inline-formula>) and reduce the specific ON-resistance (<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msub><mi mathvariant="normal">R</mi><mrow><mi>on</mi><mo>,</mo><mi>sp</mi></mrow></msub></semantics></math></inline-formula>) of 4H-SiC planar power MOSFETs. The Dod and the octagonal (Oct) cells are used in the layout design of the 650 V SiC MOSFETs in this work. The experimental results confirm that the Dod-cell MOSFET achieves a 2.2× lower <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msub><mi mathvariant="normal">R</mi><mrow><mi>on</mi><mo>,</mo><mi>sp</mi></mrow></msub></semantics></math></inline-formula>, 2.1× smaller high-frequency figure of merit (HF-FOM), higher turn on/off dv/dt, and 29% less switching loss than the fabricated Oct-cell MOSFET. The results demonstrate that the Dod cell is an attractive candidate for high-frequency power applications.