Find in Library
Search millions of books, articles, and more
Indexed Open Access Databases
Performance Enhancement in N<sub>2</sub> Plasma Modified AlGaN/AlN/GaN MOS-HEMT Using HfAlO<sub>X</sub> Gate Dielectric with Γ-Shaped Gate Engineering
oleh: Shun-Kai Yang, Soumen Mazumder, Zhan-Gao Wu, Yeong-Her Wang
Format: | Article |
---|---|
Diterbitkan: | MDPI AG 2021-03-01 |
Deskripsi
In this paper, we have demonstrated the optimized device performance in the Γ-shaped gate AlGaN/AlN/GaN metal oxide semiconductor high electron mobility transistor (MOS-HEMT) by incorporating aluminum into atomic layer deposited (ALD) HfO<sub>2</sub> and comparing it with the commonly used HfO<sub>2</sub> gate dielectric with the N<sub>2</sub> surface plasma treatment. The inclusion of Al in the HfO<sub>2</sub> increased the crystalline temperature (~1000 °C) of hafnium aluminate (HfAlO<sub>X</sub>) and kept the material in the amorphous stage even at very high annealing temperature (>800 °C), which subsequently improved the device performance. The gate leakage current (I<sub>G</sub>) was significantly reduced with the increasing post deposition annealing (PDA) temperature from 300 to 600 °C in HfAlO<sub>X</sub>-based MOS-HEMT, compared to the HfO<sub>2</sub>-based device. In comparison with HfO<sub>2</sub> gate dielectric, the interface state density (D<sub>it</sub>) can be reduced significantly using HfAlO<sub>X</sub> due to the effective passivation of the dangling bond. The greater band offset of the HfAlO<sub>X</sub> than HfO<sub>2</sub> reduces the tunneling current through the gate dielectric at room temperature (RT), which resulted in the lower I<sub>G</sub> in Γ-gate HfAlO<sub>X</sub> MOS-HEMT. Moreover, I<sub>G</sub> was reduced more than one order of magnitude in HfAlO<sub>X</sub> MOS-HEMT by the N<sub>2</sub> surface plasma treatment, due to reduction of N<sub>2</sub> vacancies which were created by ICP dry etching. The N<sub>2</sub> plasma treated Γ-shaped gate HfAlO<sub>X</sub>-based MOS-HEMT exhibited a decent performance with I<sub>DMAX</sub> of 870 mA/mm, G<sub>MMAX</sub> of 118 mS/mm, threshold voltage (V<sub>TH</sub>) of −3.55 V, higher I<sub>ON</sub>/I<sub>OFF</sub> ratio of approximately 1.8 × 10<sup>9</sup>, subthreshold slope (SS) of 90 mV/dec, and a high V<sub>BR</sub> of 195 V with reduced gate leakage current of 1.3 × 10<sup>−10</sup> A/mm.