High-Performance P- and N-Type SiGe/Si Strained Super-Lattice FinFET and CMOS Inverter: Comparison of Si and SiGe FinFET
oleh: Yi-Ju Yao, Ching-Ru Yang, Ting-Yu Tseng, Heng-Jia Chang, Tsai-Jung Lin, Guang-Li Luo, Fu-Ju Hou, Yung-Chun Wu, Kuei-Shu Chang-Liao
| Format: | Article |
|---|---|
| Diterbitkan: | MDPI AG 2023-04-01 |
Deskripsi
This research presents the optimization and proposal of P- and N-type 3-stacked Si<sub>0.8</sub>Ge<sub>0.2</sub>/Si strained super-lattice FinFETs (SL FinFET) using Low-Pressure Chemical Vapor Deposition (LPCVD) epitaxy. Three device structures, Si FinFET, Si<sub>0.8</sub>Ge<sub>0.2</sub> FinFET, and Si<sub>0.8</sub>Ge<sub>0.2</sub>/Si SL FinFET, were comprehensively compared with HfO<sub>2</sub> = 4 nm/TiN = 80 nm. The strained effect was analyzed using Raman spectrum and X-ray diffraction reciprocal space mapping (RSM). The results show that Si<sub>0.8</sub>Ge<sub>0.2</sub>/Si SL FinFET exhibited the lowest average subthreshold slope (SS<sub>avg</sub>) of 88 mV/dec, the highest maximum transconductance (G<sub>m, max</sub>) of 375.2 μS/μm, and the highest ON–OFF current ratio (I<sub>ON</sub>/I<sub>OFF</sub>), approximately 10<sup>6</sup> at V<sub>OV</sub> = 0.5 V due to the strained effect. Furthermore, with the super-lattice FinFETs as complementary metal–oxide–semiconductor (CMOS) inverters, a maximum gain of 91 <i>v/v</i> was achieved by varying the supply voltage from 0.6 V to 1.2 V. The simulation of a Si<sub>0.8</sub>Ge<sub>0.2</sub>/Si super-lattice FinFET with the state of the art was also investigated. The proposed Si<sub>0.8</sub>Ge<sub>0.2</sub>/Si strained SL FinFET is fully compatible with the CMOS technology platform, showing promising flexibility for extending CMOS scaling.