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Plasma induced damage remains a critical concern in VLSI manufacturing process as a result of the introduction of the high-k and low-k dielectric layers and complicated 3D structures in advanced technology nodes. In this paper, the level of plasma induced charging distribution on a wafer is studied comprehensively. A strong correlation between the charging level and the geometry as well as densities ratio of via structures in dual damascene BEOL copper processes is found. In addition, the effect of plasma charging on Cu corrosion is studied in this paper. To investigate the root causes of such failure mode, an in-situ plasma charging recorder is embedded with RC test structures formed by Cu BEOL processes. The recorded charging current has a strong effect on the reliability levels of the via-chain resistors and backend capacitors. Experimental data suggests that plasma charging effect not only leads to gate dielectric stress on transistors but also affects the reliability performances of the copper interconnects.